A conventional digital phase frequency detector (“PFD”) of a conventional digital phase lock loop (“DPLL”) may generate too much jitter in loop bandwidth (“LBW”). For example, in a system having a serial digital interface having a 2.970 gigabit per second serial link, namely, a 3G-SDI system; PFD introduced jitter may marginalize system performance. Additionally, a core clock of an IC may not have sufficient phase resolution, and thus phase jitter may be exacerbated.
Known solutions to compensate for jitter include addition of dither and oversampling. Addition of error or dither in a DPLL loop may reduce phase error spiking, but low level loop linearity and/or “floor-level” phase noise may continue to significantly limit system performance. Use of a fast sampling clock for high-speed oversampling may be available in some ICs that allow for multiple phases of clock generation; however, some ICs may not have this capability. Furthermore, use of clock buffers and/or chip power for providing such a fast sampling clock may add cost. Along those lines, adding dither and/or oversampling may be too expensive for some applications.
Accordingly, it may be useful to provide a less expensive solution to reduce jitter than those previously described.